Systems and methods for back end of line processing of semiconductor circuits

ABSTRACT

A BEOL manufacturing process for forming a via on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a load, unload, load (LUL) process. By using a LUL process, thermal processing is minimized, which reduces Al extrusion at the via interfaces.

BACKGROUND

1. Field of the Invention

The invention relates generally to semiconductor fabrication, and moreparticularly to back end of line (BEOL) techniques that reducemanufacturing errors related to via metal extrusion

2. Background of the Invention

Semiconductor wafers are manufactured in accordance with a process flow.The process flow comprises all of the different processing steps, suchas etching and photolithography, involved in the process ofmanufacturing semiconductor wafers. A typical process flow can consistof 300-400 steps, wherein each of these steps contributes to the finalcircuit structures formed within a single chip on the semiconductorwafer. A typical process flow is divided into two main sub-processes.The first of these main sub-processes can be termed the front end ofline (FEOL) process, and the second of these main sub-processes can betermed the back end of line (BEOL) process.

The FEOL process typically starts from the laser marking of wafer lotsand continues through the formation of Shallow Trench Isolation (STI),implantation of P and N wells, etching of poly, and followed byimplantation of various regions such as the drain and source regions ofa transistor structure.

The BEOL process can comprise the formation of metal lines and viacontacts between metal lines in different layers of the wafer. Often,there are two, or more metal layers comprising metal interconnectionlines. Vias run from the FEOL layers to the first metal layer andbetween metal layers. The BEOL process is a process whereby devices inthe FEOL layers are interconnected with other circuits forming the chipand to the outside world.

Metal layers are typically formed via a Physical Vapor Deposition (PVD)process. A typical PVD process comprises the deposition of three layersof metal. These metal layers typically comprise Ti, Al or AlCu, and Tior TiN. First, for example, a Ti layer is deposited followed by thedeposition of an Al layer, and then the deposition of a TiN layer. Aseach layer is deposited, the wafer is heated up during the deposition,and then allowed to cool.

Vias are then patterned in the lower metal layers and further metallayers are formed over the lower metal layers. Conventionally, a via isformed by first forming metal adhesion layers within the patterned viahole and then forming a tungsten (W) plug inside of the metal adhesionlayers. The metal adhesion layers often comprise a Titanium (Ti) metallayer formed within the patterned via hole and a Titanium Nitride (TiN)layer formed with the Ti Layer. The Ti Layer is often formed in a firstdeposition chamber (CH 1) and the TiN layer is often formed in a seconddeposition chamber (CH 2). The Ti adhesion layer can be formed usingPVD, or more specifically Ionized Metal Plasma (IMP) PVD. The TiNadhesion layer can be formed using Metal Organic Chemical VaporDeposition (MOCVD)

It will be understood that the metal adhesion layer formation cansubject the wafer to high heat. For example, in a conventional process,the temperature in CH 1 can be as high as 200° C. and rising throughoutthe process. The temperature in CH 2 can be as high as 450° C.Unfortunately, the Al in the metal layers can melt at temperaturesaround 600° C. The back-to-back heating processes can actually cause thewafer temperature to exceed the Al melting point, which cause the Al toextrude into the via. This can increase the via resistance and lead todevice performance problems and even failures.

One solution to this problem is to reduce the heat cycle timesassociated with deposition of the Ti layers by thinning the Ti layers;however, such solutions are not ideal since it is much harder to controlPVD processes with thinner films. Thus, reducing the heat cycling timeby reducing the thickness of the Ti layers will reduce reliability aswell.

SUMMARY

A BEOL via adhesion manufacturing process comprises forming a firstportion of a metal adhesion layer, such as a Ti layer, within apatterned via and then removing the wafer from the chamber and placingit in a cooling chamber to undergo a cooling process. The wafer can thenbe placed back into the chamber for formation of the remainder of themetal adhesion layer. The wafer can then be placed into another chamberfor formation of a second metal adhesion layer, such as a TiN layer,within the patterned via. The process can be referred to as aLoad-Unload-Load (LUL) process. By using the LUL process the thermalprocessing of the wafer is minimized, which reduces Al extrusion at thevia interfaces.

These and other features, aspects, and embodiments of the invention aredescribed below in the section entitled “Detailed Description.”

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the invention, and the advantagesthereof, reference is now made to the following descriptions taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a diagram illustrating an exemplary semiconductor circuit thatcan comprise a single chip on a semiconductor wafer;

FIG. 2 is a diagram illustrating a metal layer within the circuit ofFIG. 1 in more detail; and

FIG. 3 is a Transmission Electron Microscope (TEM) image illustrating Alextrusion that can result from a conventional via formation process; and

FIG. 4 is a flowchart illustrating an example method for depositingmetal adhesion layers during via formation in accordance with oneembodiment.

DETAILED DESCRIPTION

FIG. 1 is a diagram illustrating an example semiconductor circuit 100that can comprise a single chip on a semiconductor wafer. In the exampleof FIG. 1, circuit 100 is a memory circuit comprising a main memoryportion 120 and a periphery portion 122. Main memory portion 120 cancomprise the structures that form memory circuit 100, while peripheryportion 122 can comprise the interconnects and control circuitryrequired to interfaced the main memory portion 120 with the controlcircuits and interconnects required to control and access main memoryportion 120.

It will be understood that while the systems and methods described belowwill be described in relation to a memory circuit such as circuit 100,the invention is in no way restricted to memory circuits. Rather, itwill be clear that the systems and methods described herein can beapplied to any BEOL process regardless of the type of circuit involved.Further, while there are two metal layers 108 and 110 illustrated in theexample of FIG. 1, it will be understood that the systems and methodsdescribed below can be extended to circuits with fewer or more metallayers, and that two metal layers are shown by way of example only.

Circuit 100 comprises several layers constructed using variouswell-known semiconductor processing techniques. For example, circuit 100can comprise device layer 124, which can be constructed using FEOLtechniques, and an interconnect layer 126, which can be constructedusing BEOL techniques.

Device layer 124, can comprise several sub-layers. These sub-layers caninclude a well 102, which can comprise a silicon well and variousregions, i.e., drain and source regions, implanted therein. Thesemiconductor well and implanted regions can be formed using well-knownsemiconductor techniques. A word/bit line layer 104 can then be formedon top of well layer 102. Word/bit line layer 104 can comprise variousinterconnect lines such as word lines and bit lines formed usingwell-known semiconductor techniques. A storage layer 106 can then beformed on top of word/bit line layer 104.

Interconnect layer 126 can comprise several metal layers, of which metallayer 1 108 and metal layer 2 110 are illustrated by way of example.Metal layers 108 and 110 can comprise metal contacts such as metalcontacts 128 and 130 as well as interconnecting vias, such as vias 112,114 and 116, configured to connect metal contacts 130 and 128 as shown.In addition, vias such as vias 118, 120, 121, 122, and 124, can also beincluded to connect metal contacts 128 to various layers within devicelayer 124 as illustrated.

FIG. 2 is a diagram illustrating a portion of interconnect layer 126 inmore detail. FIG. 2 illustrates a portion of interconnect layer 126surrounding via 112 in metal layer 1 108. Thus, via 112 is bounded aboveand below by metal contacts 130 and 128, respectively. As can be seen, ametal contact, such as metal contact 128, can comprise a plurality ofmetal layers. These layers can include Ti layers 206, TiN layers 210,and Al layer 208.

It will be understood that while the example of FIG. 2 metal layer 128includes Ti layers 206, TiN layers 210, and an Al layer 208, otherlayers can also be incorporated in addition, or in place of the layersillustrated in FIG. 2. For example, Al layer 208 can be replaced by anAlCu layer.

Via 112 can then comprise metal adhesion layers 214 and 216 and W plug212. For example, as explained above, metal adhesion layer 214 cancomprise a TiN layer grown using MOCVD, while metal layer 216 cancomprise a Ti layer grown using IMP PVD. If a conventional process isused to form layers 214 and 216, however, then extrusion of Al layer 208can result. This is illustrated in FIG. 3. FIG. 3 is a TEM thatillustrates Al extrusion at the lower end 304 of via 112. In the TEM ofFIG. 3, the top portion 302 of via 112 is unaffected; however, theextrusion of portion 304 can increase resistance and lower reliabilityof the connection made via vias 112.

The extrusion phenomenon illustrated in FIG. 3 occurs, because thetemperature cycle, i.e., the temperature and time, required to effectthe deposition of metal adhesion layer 214 and 216 can actually cause Allayer 208 to melt.

FIG. 4 is a diagram illustrating a process for forming a via, such asvia 112, in accordance with one embodiment of the systems and methodsdescribed herein. First in step 402, a first metal layer (metal layer 1)can be formed. The metal layer can actual comprise a plurality of metallayers as illustrated for layer 128 in FIG. 2. Thus, step 402 cancomprise the formation of a Ti layer, a TiN layer, an Al layer, a secondTi layer, and a second TiN layer. The metal layers can, for example, beformed via PVD, or more specifically IMP PVD.

In step 404 a via, such as via 112, can be patterned and in step 406 thewafer can be degassed. In step 408, the wafer can be placed into apre-cleaning chamber (PC II) and in step 410 the wafer can be removedfrom the PC II and placed into a cooling chamber (CH A).

In step 412, the wafer can be removed from CH A and placed into adeposition chamber (CH 1) in which a metal adhesion layer, e.g., Tilayer 216, can be formed in the patterned via hole; however, only aportion of the metal layer is formed. The wafer is then removed form CH1 and placed back into a cooling chamber or returned to the load lock,where the wafer is cooled again in step 414. Since Ti can adsorb oxygen,there is no native oxide issue when the wafer is exposed to theatmosphere. Then, in step 416, the wafer is placed back into CH 1 andthe remainder of the adhesion layer is formed. This is the LUL process,which can reduce the overall thermal stressing of the wafer and preventAl extrusion.

The Ti Layer can be formed using IMP PVD. For example, a Ti layer of 400Å can be formed by first forming a 200 Å layer and then forming another200 Å layer of Ti. Accordingly, the Ti layer thickness can be maintainedat a thickness of 400 Å without over stressing the wafer. Each CH 1 stepcan last for approximately 49 s at approximately 200° C. It will beunderstood, how ever, that the dimensions and temperatures provided areby way of example only and will depend on the requirements of specificimplementation.

In step 418, the wafer can then be placed in another deposition chamber(CH 2 or CH 3) for formation of a second metal adhesion layer, e.g., aTiN layer 214. The second metal adhesion layer can, e.g., be formedusing MOCVD. The CH 2 or CH 3 processing time can be approximately 177 sat a temperature of approximately 450° C.

In step 420, the wafer can be removed and placed in a second coolingchamber (CH B). A W plug can then be formed in the patterned via hole instep 422. The W plug can then be polished, e.g., using CMP, in step 424,and the second metal layer can be formed in step 426. Again, the secondmetal layer can actual comprise a plurality of metal layers asillustrated for layer 130 in FIG. 2. Thus, step 402 can comprise theformation of a Ti layer, a TiN layer, an Al layer, a second Ti layer,and a second TiN layer. The metal layers can, for example, be formed viaPVD, or more specifically IMP PVD.

Thus, by implementing the process of FIG. 4, Al extrusion can beavoided, while still maintaining Ti adhesion layer thickness, which canimprove device reliability and lower failure rates.

While certain embodiments of the inventions have been described above,it will be understood that the embodiments described are by way ofexample only. Accordingly, the inventions should not be limited based onthe described embodiments. Rather, the scope of the inventions describedherein should only be limited in light of the claims that follow whentaken in conjunction with the above description and accompanyingdrawings.

1. A method for forming via on a semiconductor wafer in a back end of the line (BEOL) process, comprising: patterning a via hole for formation of the via; forming a portion of a first metal adhesion layer in the patterned via hole; cooling the wafer; forming the remaining portion of the first metal adhesion layer in the patterned via hole; and forming a second metal adhesion layer inside the first metal adhesion layer within the patterned via hole.
 2. The method of claim 1, further comprising cleaning the wafer before forming the portion of the first metal adhesion layer.
 3. The method of claim 2, further comprising cooling the wafer after cleaning the wafer and before forming the portion of the first metal adhesion layer.
 4. The method of claim 1, further comprising cooling the wafer after forming the second metal adhesion layer.
 5. The method of claim 1, wherein forming the portion of the first metal adhesion layer comprises depositing the portion of the first metal adhesion layer within the patterned via hole.
 6. The method of claim 5, wherein the portion of the first metal adhesion layer is deposited using physical vapor deposition.
 7. The method of claim 1, wherein forming the remainder of the first metal adhesion layer comprises depositing the remainder of the first metal adhesion layer within the patterned via hole.
 8. The method of claim 7, wherein the remainder of the first metal adhesion layer is deposited using physical vapor deposition.
 9. The method of claim 1, wherein forming the second metal adhesion layer comprises depositing the second metal adhesion layer within the patterned via hole.
 10. The method of claim 9, wherein the portion of the first metal adhesion layer is deposited using metal organic chemical vapor deposition.
 11. The method of claim 1, further comprising forming a metal plug inside the first and second metal adhesion layers within the patterned via hole.
 12. A method for forming via on a semiconductor wafer in a back end of the line (BEOL) process, comprising: forming a first metal layer; patterning a via hole for formation of the via; forming a portion of a first metal adhesion layer in the patterned via hole; cooling the wafer; forming the remaining portion of the first metal adhesion layer in the patterned via hole; forming a second metal adhesion layer within the first metal adhesion layer within the patterned via hole; forming a metal plug inside the first and second metal adhesion layers within the patterned via hole.
 13. The method of claim 12, further comprising cleaning the wafer before forming the portion of the first metal adhesion layer.
 14. The method of claim 13, further comprising cooling the wafer after cleaning the wafer and before forming the portion of the first metal adhesion layer.
 15. The method of claim 12, further comprising cooling the wafer after forming the second metal adhesion layer.
 16. The method of claim 12, wherein forming the portion of the first metal adhesion layer comprises depositing the portion of the first metal adhesion layer within the patterned via hole.
 17. The method of claim 16, wherein the portion of the first metal adhesion layer is deposited using physical vapor deposition.
 18. The method of claim 12, wherein forming the remainder of the first metal adhesion layer comprises depositing the remainder of the first metal adhesion layer within the patterned via hole.
 19. The method of claim 18, wherein the remainder of the first metal adhesion layer is deposited using physical vapor deposition.
 20. The method of claim 12, wherein forming the second metal adhesion layer comprises depositing the second metal adhesion layer within the patterned via hole.
 21. The method of claim 20, wherein the portion of the first metal adhesion layer is deposited using metal organic chemical vapor deposition.
 22. The method of claim 12, wherein forming the portion of the first metal adhesion layer comprises heating the wafer to approximately 200° C.
 23. The method of claim 22, wherein forming the portion of the first metal adhesion layer comprises heating the wafer for approximately 49 seconds.
 24. The method of claim 12, wherein forming the remainder of the first metal adhesion layer comprises heating the wafer to approximately 200° C.
 25. The method of claim 24, wherein forming the remainder of the first metal adhesion layer comprises heating the wafer for approximately 49 seconds.
 26. The method of claim 12, wherein forming the second metal adhesion layer comprises heating the wafer to approximately 450° C.
 27. The method of claim 26, wherein forming the second metal adhesion layer comprises heating the wafer for approximately 177 seconds. 